1. Field of the Invention
The present invention generally relates to the field of packaging integrated circuit devices, and, more particularly, to a method of packaging integrated circuit devices using a preformed carrier.
2. Description of the Related Art
Microelectronic devices generally have a die (i.e., a chip) that includes integrated circuitry having a high density of very small components. In a typical process, a large number of die are manufactured on a single wafer using many different processes that may be repeated at various stages (e.g., implanting, doping, photolithography, chemical vapor deposition, plasma vapor deposition, plating, planarizing, etching, etc.). The die typically include an array of very small bond pads electrically coupled to the integrated circuitry. The bond pads are the external electrical contacts on the die through which the supply voltage, signals, etc. are transmitted to and from the integrated circuitry. The die are then separated from one another (i.e., singulated) by backgrinding and cutting the wafer. After the wafer has been singulated, the individual die are typically “packaged” to couple the bond pads to a larger array of electrical terminals that can be more easily coupled to the various power supply lines, signal lines and ground lines.
Electronic products require packaged microelectronic devices to have an extremely high density of components in a very limited space. For example, the space available for memory devices, processors, displays and other microelectronic components is quite limited in cell phones, PDAs, portable computers and many other products. As such, there is a strong drive to reduce the height of a packaged microelectronic device and the surface area or “footprint” of a microelectronic device on a printed circuit board. Reducing the size of a microelectronic device is difficult because high performance microelectronic devices generally have more bond pads, which result in larger ball/grid arrays and thus larger footprints.
There are many techniques of packaging integrated circuit devices. Most involve conductively coupling a substrate, e.g., a printed circuit board, an interposer, etc., to the integrated circuit chip using a plurality of wire bonds. Thereafter, the chip and substrate are positioned in a mold and an injection molding process is typically performed to encapsulate the chip and the substrate in an encapsulant material, e.g., molding compound, epoxy, etc. The process described above, while acceptable in many applications, still suffers from said drawbacks. For example, products may have to be scrapped due to problems encountered in the molding process, e.g., voids. Moreover, the process described above may be very labor-intensive in that it requires that the molding apparatus be frequently cleaned.
The present invention is directed to a device and various methods that may solve, or at least reduce, some or all of the aforementioned problems.